[Indigo]<Alto-1822>AIupdate.memo!1

Proposed Alto-1822 Interface, Update

Page Numbers: Yes X: 527 Y: 10.5"

Inter-Office Memorandum

ToTaft, Boggs, Shoch,DateJanuary 26, 1978
Strollo, Stewart

FromLarry StewartLocationPalo Alto

SubjectAlto-1822 InterfaceOrganizationSSL

New microcode, other changes

Filed on: [Maxc1]<LStewart>AIupdate.press

John Shoch, Ed Taft, Dave Boggs, and I got together on January 10 to look over the proposed Alto-1822 design. This memo presents an updated view of the interface software and microcode with some of the bugs fixed. Not included here is a better description of the PROM contents.

Emulator - Task interface

An emulator program can wake up the IMP task by executing an SIO instruction with either or both of AC0 bits 5 and 6 set. Possible functions are start receiver, start transmitter, and read status/set control register. AC1 is must point to a command block during the execution of the Read Status / Set Control Register SIO. The task saves the control block pointer in an S register for later use. This means that a read status call must be made before trying to do a data transfer.

Due to the shortage of S registers, we decided to keep all the 1822 interface buffer pointers in main memory. This reduces the number of required S registers to one, but in exchange, requires three main memory cycles per word. The single S register contains a pointer to the 12 word control block. The single control block contains entries for input, output, and control functions.

Control Block Structure

CmdBlock:struct
[
inputPointer/next word to be used
inputBufferEnd/first word not in buffer
outputPointer/next word to be used
outputBufferEnd/first word not in buffer
controlWord/command
blank
lvInputPost/input post location
inputIntBits/input interrupt channels
lvOutputPost/output post location
outputIntBits/output interrupt channels
lvControlPost/control post location
controlIntBits/control interrupt channels
]

The receiver will go off and collect a packet from the IMP. The final buffer location used is returned in lvBuffer. Returns error if the buffer size is zero, if the buffer overflowed, or if the receiver seems to be running already.

The transmitter will send a packet (buffer) to the IMP without further attention. Returns error if the buffer size is zero or if the transmitter seems to be running already.

Read Status / Set Control Register

This command allows an emulator program to observe the interface without disturbing it. The command word can do things like reset the interface to ground zero, turn on the Host Ready relay, etc.

LDAAC0,#003000
LDAAC1,CmdBlock
SIO

After the style of the ethernet, on completion of a command, the microcode status occupies the left byte of the Post location and the hardware status occupies the right byte.

Possible microcode status bytes:
00000001-all ok
00000010-input hardware seemed to be busy already
00000011-output hardware seemed to be busy already
00000100-buffer overflow (input only)
00000101-input buffer length was zero on entry
00000110-input buffer length was zero on entry

Hardware status bits:
struct
[
unusedbit5;
IMPWasDownbit1;
IMPnotReadybit1;
HostnotReadybit1;
]

The command word is used to set and clear some control flipflops in the hardware. Some of these, like TestMode and HostReadyRelay, will never be touched by the microcode - they are to be used by an emulator program. Others, like SetLastWord, are intended to be used only by the microcode and should never appear in a command.

Command Bits:
struct
[
unusedbyte;
turnOnReadyRelaybit;
turnOffReadyRelaybit;
turnOnTestModebit;
turnOffTestModebit;
unusedbit;
resetWorldbit;
setLastWordbit;
tryClearingIMPdownFlopbit;
]

A copy of the updated microcode is attached. The code uses one S register. I include here a table of timing information. A ’+’ indicates a TASK.

OperationMicrocycles

Emulator control/status call15
Emulator input request17
(Buffer length zero)
Emulator input request12
(Buffer length non-zero)
Emulator output request9+8
(Buffer length zero)
Emulator output request9+20
(Buffer length non-zero)
Input wakeup(Buffer Overflow)20
Input wakeup(Normal)19
Input wakeup(Last word)18+8(wierd kludge)
Output wakeup(Normal)20
Output wakeup(Last word)20
Output wakeup(Normal end)19

; Alto 1822 Interface microcode
; Larry Stewart 12/26/77
; Updated 1/26/77

; 2-way branches using NEXT9
!1,2,IODMOR,IODEND
!1,2,INXT,IODLST
!1,2,IIDMOR,IIDFUL
!1,2,IIBLOK,IIBLZ
!1,2,IOBLOK,IOBLZ

; 2-way branch using NEXT7 (Caused by IREAD)
%4,4,0,IIDCON,IIDLST

; 16-way dispatch using NEXT4,NEXT5,NEXT6,NEXT7
%74,74,0,INOCMD,IODATA,IIDATA,IIDATB,IOSTRT,IOBAD,IOSTA,IOBADA,IISTRT,IISTA,IIBAD,IIBADA,ICTST,ICTSTA,ICTSTB,ICTSTC;

; Task Specific Function Definitions

$IREAD $ ; F2-8Input data
$IWRITE$ ; F2-12Output data
$IOCLR $ ; F1-9Clear hardware output wakeup
$ISWAKC$ ; F1-10Clear SIO generated wakeup
$IIENBL$ ; F2-10Start read (turn on RFNIB)
$IBRNCH$ ; F1-1116-way branch on wakeup conditions
$IPOSTF$ ; F2-11Post function (gate status to bus)
$ISETCS$ ; F2-9Set control functions from bus

;R (S) registers NOTE: WHAT REGISTER?

$ICBPTR$R1;Control Block Pointer
;$MTEMP $R25Temporary storage
; Task constants

$ISDON $777;done
$ISIBAD$1377;input busy
$ISOBAD$1777;output busy
$ISOVF $2377;buffer overflow (input only)
$ISIBLZ$2777;input block length zero
$ISOBLZ$3377;output block length zero

; Other definitions

$AC1 $R2;Emulator register

;Main loop. Task waits here when not processing something.

IMLOOP:T← ICBPTR,IBRNCH;start a data ptr cycle
L← 2+T,:INOCMD;16-way branch

;[INOCMD,IODATA,IIDATA,IIDATB,IOSTRT,IOBAD,IOSTA,IOBADA,
; IISTRT,IISTA,IIBAD,IIBADA,ICTST,ICTSTA,ICTSTB,ICTSTC]

INOCMD:TASK,:INXT;;Can’t get here!
;NOTE: HOW SHOULD THIS WORK?

;Read status and set control register

ICTST:L← T← AC1,:ICTSTM;
ICTSTA:L← T← AC1,:ICTSTM;
ICTSTB:L← T← AC1,:ICTSTM;
ICTSTC:L← T← AC1,:ICTSTM;
ICTSTM:MAR← 4+T;Start fetch of args
ICBPTR← L;Save ctl block pointer
T← 12,ISWAKC;post location offset
L← ISDON;Set control flops
ISETCS← MD,:IPOST;Control done

;Common Post routine
; Expects offset of post location in T
;and task status in L

IPOST:MAR← ICBPTR+T;Start double reference
MTEMP← L;Save ucode status
T← NWW;
MD← MTEMP,IPOSTF;Bus AND hardware status
L← MD OR T,TASK;NWW OR interrupt bits
NWW← L,:IMLOOP;

;If a hardware input/output wakeup turns up along with a
;SIO start input/output request, something is awry...

IIBADA:T← 6,:IIBADM;
IIBAD:T← 6,:IIBADM;
IIBADM:L←ISIBAD,ISWAKC,:IPOST;
IOBADA:T← 10,:IOBADM;
IOBAD:T← 10,:IOBADM;
IOBADM:L← ISOBAD,ISWAKC,:IPOST;Clear wakeup

;Input initialization

IISTRT:MAR← T,:IISTM;compute final addr addr
IISTA:MAR← T,:IISTM;
IISTM:T← MD;read data pointer
L← MD-T;
SH=0,ISWAKC;clear wakeup
T←6,:IIBLOK;[IIBLOK,IIBLZ]
IIBLOK:IIENBL,TASK,:INXT;length ok,start reader
INXT::IMLOOP;continue

IIBLZ:L← ISIBLZ,:IPOST;

;Input Main loop

IIDATA:MAR← T,:IIDATM;Start fetch
IIDATB:MAR← T,:IIDATM;
IIDATM:T← MD;get pointer
L← MD-T;past end of buffer?
MAR← T;start data fetch
L← 1+T,SH=0;
MTEMP← L,:IIDMOR;[IIDMOR,IIDFUL]

IIDMOR:MD← IREAD;Read and branch on last word.
;Except on the last word, this
;clears the wakeup
MAR← ICBPTR,:IIDCON;[IIDCON,IIDLST]

IIDCON:IIENBL;enable receiver
MD← MTEMP,TASK,:INXT;update ptr,restart

IIDLST:L← ISIDON,TASK;this TASK only works
;because the hardware doesn’t really clear the
;wakeup until the next IREAD in this case
MD← MTEMP;update pointer
IIDPST:T← 6;post offset
SINK← IREAD,:IPOST;clear wakeup (again)

IIDFUL:L← ISIOVF,:IIDPST;overflow status

;Output initialization

IOSTRT:MAR← 2+T,:IOSTM;Start fetch
IOSTB:MAR← 2+T,:IOSTM;
IOSTM:T← MD;test for zero length
L← MD-T,TASK;
SH=0;clear wakeup
T← 10,:IOBLOK;[IOBLOK,IOBLZ]
IOBLOK:T← ICBPTR,ISWAKC,:IODATA;clr wakeup, send data

IOBLZ:L← ISOBLZ,ISWAKC,:IPOST;

;Main output loop

IODATA:MAR← L← 2+T,:IODATM;start fetch
IODATB:MAR← L← 2+T,:IODATM;
IODATM:MTEMP← L;save cb ptr
T← MD;get pointer
L← MD-T;past end of buffer?
MAR← MTEMP,SH=0;save data pointer
MTEMP← L,:IODMOR;update ptr [IODMOR,IODEND]

IODMOR:L← MTEMP-1;
MD← 1+T;
MAR← T;start data fetch
IWRITE← MD,SH=0;clear wakeup, last?
TASK,:INXT;[INXT,IODLST]

;Set last word flop in order to set Last Host Bit

IODLST:SINK← 2,ISETCS,:IMLOOP;

IODEND:T← 10;
L← ISDON,IOCLR,:IPOST