; MesaGateCPChain1822.mu -- Top-level microcode source for Alto Gateway ; running Mesa and using CommProc, Alto-1822, and ; 3 copies of Chained Ethernet microcode. ; Last modified HGM June 29, 1980 10:45 PM, Delete PREncrypt (won't fit) ; Last modified HGM May 13, 1980 11:30 PM, Upgrade to Mesa 6. ; Last modified HGM March 28, 1979 11:07 PM #AltoConsts23.mu; ; Reset locations of the tasks to be started in the Ram. ; 0 Emulator ; 1 Ethernet 2. Note that this is the task normally used for ; the CommProc interval timer. If Ethernet 2 is actually to ; be used, the interval timer wakeup and active signals ; must be disconnected. ; 2 Ethernet 1 ; 5 Alto-1822 interface ; 6 CommProc ; 7 Ethernet 0 (standard) ; 10 Memory Refresh task ; 11 Display Word task ; 12 Cursor task ; 13 Display Horizontal task ; 14 Display Vertical task !17, 20, Emulator, 2EREST, 1EREST, , , IMLOOP, CommProcTask, 0EREST, MRT, DWT, CURT, DHT, DVT; ; Ram entry vector, for access via Mesa JRAM instruction. ; Note that only Ram locations 400-777 and 1400-1777 are reachable from Rom1. %7, 1777, 1400, SilentBoot, SetLineTab, PupChecksum, ChangeControlReg; %7, 1777, 1420, SetConPtr; ; Reserve 774-1003 for Ram Utility Area. ; These are assigned below to otherwise unlabelled instructions executed ; only by the Emulator task. %7, 1777, 774, RU774, RU775, RU776, RU777, RU1000, RU1001, RU1002, RU1003; ; ; Now bring in Mesa overflow microcode (From XMesaOverflow.mu) ; #XMesaRAM.mu; ;----------------------------------------------------------------- ; MISC - Miscellaneous instructions specified by alpha ; alpha=11 => RCLK has been handled by ROM ; T contains alpha on arrival at MISC in RAM ;----------------------------------------------------------------- ; Precisely one of the following lines must be commented out. MISC: L←0, SWMODE, :Setstkp; dummy MISC implementation ;#MesaMisc.mu; real implementation ; **** Modified standard tasks **** #CPDispMRT.mu; Memory refresh task -- interval timer and ; cursor processing removed #GateDisplay.mu; Display and cursor tasks using 2 fewer R registers ; than the standard microcode ; **** CommProc microcode **** #CommProc1.mu; Only main dispatch, subroutines, and BiSync interface ; Suppress "unused predef" warnings caused by not including CommProc2.mu. ; If we ever run short of Ram, assign these to real, otherwise unlabelled ; instructions elsewhere. RCAAT: NOP; TCAAT: NOP; TUIdl: NOP; TUBlk: NOP; EPRet2: NOP; ESRet2: NOP; ESRet3: NOP; EPRet3: NOP; ; **** Chained Ethernet microcode **** ; Standard Ethernet board $0ECNTR $R12; Standard R-registers $0EPNTR $R13; $0ELOC $600; Standard control block address (600-611) #ChainEther0.mu; ; First extra Ethernet board $1ECNTR $R11; Same as CLOCKTEMP, which has been abolished $1EPNTR $R14; Not used by Mesa or Nova emulator $1ELOC $630; Control block address (630-641) #ChainEther1.mu; ; Second extra Ethernet board $2ECNTR $R21; Same as CURDATA, freed by special cursor microcode $2EPNTR $R26; Same as HTAB, freed by special display microcode $2ELOC $642; Control block address (642-653) #ChainEther2.mu; ; **** Emulator Task **** ; Emulator, SilentBoot and PupChecksum #PupChecksum.mu; ; SetLineTab: PROCEDURE[lineTab: POINTER] ; Specifies the address of the Line Table (LINTAB). ; Entry point is Ram address 1401. SetLineTab: L← stk0; LINTAB← top of stack RU774: LINTAB← L; RU775: L← 0, TASK; Empty the stack RU776: stkp← L, :Emulator; ; ChangeControlReg: PROCEDURE[lineTimes4: CARDINAL, changeMask: WORD] ; Changes (sets or resets) bits in the control word for a line. ; The change is atomic with respect to CommProc task execution. ; lineTimes4: 4 times the line number to be affected. ; changeMask: Bits 4:15 are a mask of bits to be affected and bit 0 is ; the desired new value of those bits. ChangeControlReg: L← 0, TASK; Empty the stack (TASK vital here) RU777: stkp← L; RU1000: L← stk0; lineTimes4 RU1001: LINE*4← L; RU1002: T← stk1; T← changeMask RU1003: L← LCRetX#, :LIMCon0; L← LIMCon0 return index LCRetX: :Emulator; ; **** Alto-1822 support **** ; Alto-1822 interface microcode. ; Must follow emulator stuff because it contains a Ram subroutine. #Mesa1822.mu;