;----------------------------------------------------------------- ; MesaXRAM.Mu - Overflow from Mesad.mu residing in RAM ; Last modified by Levin - August 2, 1978 8:39 AM ;----------------------------------------------------------------- ; Separate assembly requires... #MesabROM.mu; ;----------------------------------------------------------------- ; BLT - block transfer ; assumes stack has precisely three elements: ; stk0 - address of first word to read ; stk1 - count of words to move ; stk2 - address of first word to write ; the instruction is interruptible and leaves a state suitable ; for re-execution if an interrupt must be honored. ;----------------------------------------------------------------- %1,1777,402,BLTintpend,BLTloop; BLTloop must match ramBLTloop %1,1777,404,BLTnoint,BLTint; BLTint must match ramBLTint !1,2,BLTmore,BLTdone; !1,2,BLTsource,BLTCsource; !1,2,BLTeven,BLTodd; !1,1,BLTintx; shake branch from BLTloop !1,1,Setstkp; shake IDISP from BLTnoint ; Entry sequence in ROM1; actual entry is at BLTloop ;BLT: stk7_L, SWMODE, :BLTx; stk7=0 <=> branch pending ;BLTx: IR_msr0, :ramBLTloop; IR_ is harmless BLTloop: L_T_stk1-1, BUS=0, :BLTnoint; BLTnoint: stk1_L, L_BUS AND ~T, IDISP, :BLTmore; L_0 on last iteration (value ; on bus is irrelevant, since T ; will be -1). IDISP on last ; cycle requires that Setstkp ; be odd. BLTmore: T_cp, :BLTsource; BLTsource: MAR_stk0, :BLTupdate; start data source fetch BLTCsource: XMAR_stk0+T, :BLTupdate; start code source fetch BLTupdate: L_stk0+1; stk0_L; update source pointer L_stk2+1; T_MD; source data MAR_stk2; start dest. write stk2_L, L_T; update dest. pointer SINK_NWW, BUS=0, TASK; check pending interrupts MD_M, :BLTintpend; loop or check further BLTintpend: SINK_wdc, BUS=0, :BLTloop; check if interrupts enabled ; Must take an interrupt if here (via BLT or BITBLT) BLTint: SINK_stk7, BUS=0, :BLTintx; test even/odd pc BLTintx: L_mpc-1, :BLTeven; prepare to back up BLTeven: mpc_L, L_0, :BLTodd; even - back up pc, clear ib BLTodd: ib_L, SWMODE; odd - set ib non-zero :romIntstop; ; BLT completed BLTdone: SINK_stk7, BUS=0, SWMODE, :Setstkp; stk7=0 => return to 'nextA' Setstkp: stkp_L, :romnext; 'next' has proper SWMODE bit