AU
;File=DDTape-Rev-C.sil Rev=C Date=2/10/81 Reference  MARKED BUILT 
;File=DDTape01.sil Rev=C Date=12/18/80 Page=02  MARKED BUILT 
;File=DDTape02.sil Rev=C Date=12/18/80 Page=03  MARKED BUILT 
;File=DDTape03.sil Rev=C Date=2/10/81 Page=04  MARKED BUILT 
;File=DDTape04.sil Rev=C Date=2/10/81 Page=05  MARKED BUILT 
;File=DDTape05.sil Rev=C Date=12/09/80 Page=06  MARKED BUILT 
;File=DDTape06.sil Rev=C Date=2/10/81 Page=07  MARKED BUILT 
;File=DDTape07.sil Rev=C Date=12/18/80 Page=08  MARKED BUILT 
;File=DDTape08.sil Rev=C Date=12/18/80 Page=09  MARKED BUILT 
;File=DDTape09.sil Rev=C Date=12/16/80 Page=10  MARKED BUILT 
;File=DDTape10.sil Rev=C Date=1/28/81 Page=11  MARKED BUILT 
;File=DDTape11.sil Rev=C Date=12/18/80 Page=12  MARKED BUILT 
;File=DDTape12.sil Rev=C Date=12/09/80 Page=13  MARKED BUILT 
;File=DDTape13.sil Rev=C Date=12/09/80 Page=14  MARKED BUILT 
;File=DDTape14.sil Rev=C Date=1/28/81 Page=15 Reference  MARKED BUILT 
; Implicitly generated wiring ...

@

CALIBRATE: <1>   ; INSTALL welder nose, board Component side up ...
    E61 {12,0}            C122 {12,396}         C62 {252,396}         E1 {252,0}

UNPLUG: <2>
    #a12.1i {224,384}     #a56.1i {48,384}      #c7.1i {244,360}      #e24.1i {176,336}
    #e61.1i {28,336}      #g38.1i {120,312}     #g54.1i {56,312}      #g62.1i {24,312}

CALIBRATE: <3>   ; INSTALL welder nose, board Wiring side up ...
    C122 {12,0}           E61 {12,396}          E1 {252,396}          C62 {252,0}

DELETE: <4> ; DDTape03.sil+10
    #g38.2i {116,84}      #g38.3i {112,84}      #g62.1i {24,84}       #g62.4i {12,84}
    #e61.5o {12,60}       #a56.16o {32,24}



DELETE: <5> ; DDTape04.sil+9
    #g54.1i {56,84}       #c7.6o {224,36}



DELETE: <6> ; DDTape06.sil+9
    #a12.11i {188,24}     #e24.15o {164,72}



CALIBRATE: <7>   ; INSTALL welder nose, board Wiring side up ...
    C122 {12,0}           E61 {12,396}          E1 {252,396}          C62 {252,0}

DDTape03.sil+10: <8> (164)
    #g38.3i {112,84}      #g62.1i {24,84}       #g62.4i {12,84}       #a56.16o {32,24}

DDTape03.sil+12: <10> (111)
    #g38.2i {116,84}      #e61.5o {12,60}

DDTape06.sil+10: <11> (137)
    #g54.9i {36,96}       #e24.15o {164,72}

DDTape06.sil+11: <12> (186)
    #a12.11i {188,24}     #g54.8o {32,96}

WriteDataLate: <9> (211)
    #c7.6o {224,36}       #g54.1i {56,84}       #g54.10i {40,96}