// // External definitions for Asim // last edited September 28, 1978 12:33 PM // external // entry points [ InitAsim // (altotype [1], extrarom [false], extramemory [false], doublestore[false]) Asim // () -> 0/errorstring ] external // the microprocessor state [ @t // T @tu // T undefined flag (true or false) @l // L @lu // L undefined flag (true or false) @ir // IR @carry // emulator carry (0 or 1) @bus // temp. for bus data @alu // temp. for ALU output @sh // temp. for shifter output @skip // SKIP (0 or 1) @alucy // last ALU carry (0 or 1) @mar // last memory address @altbank // (XM) true iff last MAR_ selected alternate bank @mstate // memory state @marmod // 0 or 1 to OR (Alto I) or XOR (Alto II) with Mar for next reference @md // (Alto II) memory data addressed by MAR @mdx // (Alto II) memory data addressed by MAR XOR 1 @mdu // (Alto II) MD undefined flag (true or false) @nmod // modifiers for NEXT @pc // (microinstruction) PC @waiting// TASK, RDRAM, WRTRAM, SWMODE waiting or -1 @ramadr // RAM address ]